Memory devices can include internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
During a typical prior art programming operation of a flash memory cell, a selected word line coupled to the selected memory cell to be programmed is biased with a series of incrementing voltage programming pulses that start at an initial voltage that is greater than a predetermined programming voltage (e.g., approximately 16V). The programming pulse increases a charge level, thereby increasing the cell's threshold voltage Vt, on a floating gate of the memory cell. After each programming pulse, a verification operation with a word line voltage of 0V is performed to determine if the cell's threshold voltage has increased to the desired programmed level.
Immediately after programming, the floating gate can experience multiple forms of charge loss that occur at the time of ion implantation that can cause defects in the data retention characteristics of the floating gate. These include single bit charge loss, intrinsic charge loss, and quick charge loss.
Single bit charge loss is the result of a defective memory cell that exhibits electron leakage. This leakage can be accelerated with voltage or high temperature stress and results in inferior data retention.
Intrinsic charge loss is an immediate leakage of electrons from the floating gate, closest to the tunnel oxide, after a programming pulse. The trapped charge initially causes the cell Vt to appear higher than the floating gate is programmed. The leakage of these electrons after programming then causes a one time shift in the threshold voltage.
Quick charge loss also causes an immediate Vt shift after a programming pulse. Quick charge loss is the result of electrons trapped in the tunnel oxide layer after the programming pulse moving back into the channel region. When a cell passes the verify operation, the cell is inhibited from further programming and quick charge loss begins. When the cell is read after the program operation has been completed, the cell has a Vt that is lower than the Vt obtained during the program verify operation. This can require an enlargement of the Vt distribution in order to accommodate all possible threshold voltages for a given state.
FIG. 1 shows a plot of VWL versus time of a typical prior art programming operation with the accompanying real and ideal minimum/maximum threshold voltage of the target cell. The upper plot 100 shows the series of incrementally increasing programming pulses 101 being applied to the target cell as the word line voltage VWL. After each programming pulse 101, a verify pulse 102 occurs at a Vvfy level.
The lower plot 110 shows the resulting Vt of the target cell being programmed. The top Vt plot 112, 116 is the maximum threshold voltage of the target cell and the lower Vt plot 111, 114 is the minimum threshold voltage of the target cell as illustrated in FIG. 2. As the programming pulses 101 of the first plot 100 are applied to the target cell control gate, the Vt 111, 112 increases to approximately the Vt—vfy level. Once at this level, the target cell is verified and inhibited from further programming. The ideal Vt 113, 115 is shown staying level at Vt. However, the real Vt 114, 116 of the target cell begins to decrease almost immediately after the last programming pulse.
FIG. 2 illustrates a typical prior art Vt distribution of programmed cells in accordance with the Vt plot of FIG. 1. In FIG. 2, the dotted line 200 represents the ideal distribution while the solid line 201 represents the real distribution. The lower end 205 of the ideal distribution 200 corresponds to the lower ideal Vt plot 113 of FIG. 1 and the upper end 210 of the ideal distribution 200 corresponds to the upper ideal Vt 115. Similarly, the lower end 206 of the real distribution 201 corresponds to the lower real Vt plot 114 and the upper end 207 of the real distribution 201 corresponds to the upper real Vt plot 116.
The lower end of the ideal distribution 200 is verified at the Vpgm—vfy voltage. After the programming operation and subsequent inhibition of the target cell, the distribution shifts in the negative direction by an amount equal to VQCL and ends at the lower Vt 206. Such a shift in the distribution would necessitate an enlarged distribution that starts at the real lower Vt 206 and extends to the ideal upper Vt 210.
In a single level cell (SLC), a Vt distribution enlargement does not have much affect on the reading of a programmed memory cell. However, in a multiple level cell (MLC) memory cell, the state distributions are typically more closely spaced in order to fit all of the states within a low supply voltage range. Enlarging the Vt distributions in an MLC device can thus reduce the number of states that are programmable into the device. Additionally, the enlarged Vt distributions can overlap and result in errors in reading the different states.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to reduce charge loss in a memory device.